High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study

Sustained memory bandwidth for a range of access patterns is a key to high-performance vector processing. Interleaving is a popular way of constructing a high-bandwidth memory system. However, for some access patterns conflicts reduce the bandwidth of a standard, low-order interleaved memory. To improve memory bandwidth for a wide range of access patterns, alternate interleaving schemes must be considered. This paper studies a family of alternate interleaving schemes called permutation-based interleaving schemes. Permutation-based interleaving schemes can be implemented with a small amount of additional hardware and with a minimal time overhead. A detailed simulation analysis been carried out in this paper. The simulation analysis suggests that, with adequate buffering, permutation-based interleaving schemes similar to those studied in this paper can be used to implement a high-bandwidth memory system for vector processors. The resulting memory system sustains its bandwidth for a wide variety of access patterns and for large bank busy times far better than a memory system with standard interleaving.